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Alif Semiconductor /AE512F80F5582AS_CM55_HE_View /I2C0 /I2C_ENABLE_STATUS

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Interpret as I2C_ENABLE_STATUS

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (Val_0x0)IC_EN 0 (Val_0x0)SLV_DISABLED_WHILE_BUSY 0 (Val_0x0)SLV_RX_DATA_LOST

SLV_RX_DATA_LOST=Val_0x0, SLV_DISABLED_WHILE_BUSY=Val_0x0, IC_EN=Val_0x0

Description

Enable Status Register

Fields

IC_EN

The CPU can safely read this bit anytime. When this bit is read as 0x0, the CPU can safely read SLV_RX_DATA_LOST bit and SLV_DISABLED_WHILE_BUSY bit.

0 (Val_0x0): I2C is deemed completely inactive

1 (Val_0x1): I2C is deemed to be in an enabled state
SLV_DISABLED_WHILE_BUSY

Slave Disabled While Busy (Transmit, Receive). This bit indicates if a potential or active slave operation has been aborted due to the setting I2C_ENABLE[ENABLE] bit from 0x1 to 0x0. This bit is set when the CPU writes a 0x0 to the I2C_ENABLE register while:

  • I2C is receiving the address byte of the Slave-Transmitter operation from a remote master;
  • Address and data bytes of the Slave-Receiver operation from a remote master; When read as 0x1, I2C is deemed to have forced a NACK during any part of an I2C transfer, irrespective of whether the I2C address matches the slave address set in I2C (I2C_SAR register) OR if the transfer is completed before I2C_ENABLE is set to 0x0 but has not taken effect. If the remote I2C master terminates the transfer with a STOP condition before the I2C has a chance to NACK a transfer, and I2C_ENABLE[ENABLE] has been set to 0x0, then this bit will also be set to 0x1. When read as 0x0, I2C is deemed to have been disabled when there is master activity, or when the I2C bus is IDLE. The CPU can safely read this bit when IC_EN bit is read as 0x0.

0 (Val_0x0): Slave is disabled when it is IDLE

1 (Val_0x1): Slave is disabled when it is active
SLV_RX_DATA_LOST

Slave Received Data Lost. This bit indicates if a Slave-Receiver operation has been aborted with at least one data byte received from an I2C transfer due to the setting I2C_ENABLE[ENABLE] bit from 0x1 to 0x0. When read as 0x1, I2C is deemed to have been actively engaged in an aborted I2C transfer (with matching address) and the data phase of the I2C transfer has been entered, even though a data byte has been responded with a NACK. If the remote I2C master terminates the transfer with a STOP condition before the I2C has a chance to NACK transfer, and I2C_ENABLE[ENABLE] has been set to 0, then this bit is also set to 0x1. When read as 0x0, I2C is deemed to have been disabled without being actively involved in the data phase of a Slave-Receiver transfer. The CPU can safely read this bit when IC_EN is read as 0x0.

0 (Val_0x0): Slave RX data is not lost

1 (Val_0x1): Slave RX data is lost

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Register License

THIS SOFTWARE IS PROVIDED “AS IS”. NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. ALIF SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data